The assignee of the present application has developed RapidChip™ technology that lets designers quickly and affordably create high-performance, complex, customized ICs. RapidChip is a chip building technique that dramatically lowers cost, risk and time-to-market. Each RapidChip™ slice is a pre-manufactured, pre-verified chip at the density and power of an ASIC in which all silicon-based layers have been built, leaving the top metal layers to be completed with the customer's unique intellectual property. The customer selects a desired slice that best accommodates their application, and then use a software tool suite to create a proprietary design, called an instance, using the gates on the final metal layers of the chip. The result is a completed chip with near ASIC performance and density, done in the time it takes to do an FPGA, yet at much lower unit cost.
The RapidChip procedure includes the following steps: 1) an IC manufacturer provides one or more pre-built slices; 2) a customer creates a custom design by selecting what components of the slice will be used in the instance; and 3) the custom design is prepared for handoff to the IC manufacturer with a RapidWorx™ design suite.
The fundamental technology used in the RapidChip technology is the metal customization of a partially manufactured semiconductor device, called a slice, in which all silicon layers have been fabricated. Each slice incorporates diffused memory blocks, PLLs, IP blocks from a CoreWare® library, configurable transistor fabric, and an I/O ring made up of configurable and dedicated I/Os for specific requirements.
RapidReady Coreware, referred to herein as coreware, allows for integration of additional third party IP blocks (cores). A common methodology among all coreware reduces the time to design by simplifying the integration process. Coreware can be delivered in several forms to optimize for performance or flexibility: diffused, hard, firm, or soft.
Diffused coreware is fixed, pre-built, and verified in the RapidChip silicon platform and has the same high performance specifications as a cell-based ASIC. Examples of diffused IP blocks, or cores, include transceivers, PLLs, and ARM® CPUs. Examples of firm or soft IP are PCS macros, Ethernet MACs, and memory controllers. Diffused and hard coreware cores are delivered to RapidChip designers as an abstracted timing model. Soft RapidReady IP is delivered as Register Transfer Level (RTL). It provides maximum flexibility since it is synthesized during the physical synthesis step in the RapidWorx design system.
Coreware simulation models are delivered in RTL. As is well known in the art, RTL is a high-level hardware description language for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, and control logic. The most popular RTL languages are VHDL and Verilog. RTL specifications are turned into gate-level netlists.
FIG. 1 is a diagram illustrating the RapidChip design flow to create a custom instance from a slice by the IC manufacturer. First, the customer enters initial design parameters in order to populate the design-specific database, and imports customer-specific or third party cores and intellectual property (IP) to establish circuit logic (step 50). RapidWorx™ tools are then used to wire together the logic with third party tools (step 52). The RapidWorx tools provide a graphical user interface to a suite of tools that guides the designer through RTL design, analysis and synthesis to placed netlist handoff. In the design completion (step 54), the designer invokes EDA tools to simulate the finished design, decides if the design meets requisite timing goals, and performs cell placement and interconnect routing (step 54). Manufacturing (step 56), is where the designer performs final validation and releases the design to manufacturing.
FIG. 2 is a flow diagram illustrating the RapidWorx tools in further detail. The RapidWorx design system flow includes five basic steps. Each step is executed by a tool launched from the RapidWorx design system. The RapidWorx design system enables cross-probing between tools.
RapidBuilder is a tool that configures the Memories, I/Os, and clocks. RapidBuilder automatically generates RTL for them and managing integration into the slice. Test implementation and vector generation is completely automated with no intervention by the customer required.
RapidView is a tool that provides a floorplan view of the slice resources, allowing the designer to choose which memories, IO, PLL and other to allocate to which desired function. It has cross-probing capabilities with other RapidWorx tools.
RapidPRO is a tool that Allows Physical RTL optimization. RapidPRO checks the designer's RTL against best-practice design & implementation rules to find problematic RTL structures that create congestion and timing closure bottlenecks. This tool combines LSI Logic's RapidChip PRO Rule Set with Tera Systems TeraForm-RC to check RTL code for rule conformance.
Amplify RapidChip is a physical synthesis tool that combines RTL synthesis, placement, and optimization in a single integrated process.
RapidCheck is a tool that performs handoff rule checking. RapidCheck verifies a RapidChip netlist and database, and generates all outputs necessary for handoff to LSI Logic for layout completion and manufacturing. Handoff iterations are avoided because physical issues are addressed in the pre-built RapidChip slices and the correct-by-construction RapidWorx methodology.
One of the major challenges facing designers of application-specific integrated circuits (ASIC) is ensuring that the IC is testable. Because of this, design-for-test (DFT) techniques are becoming more common practice as the complexity of devices increases. IC's are becoming system-on-chip (SoC), with embedded blocks and structures that all require test and debug. Structures such as memory BIST, logic BIST, test structures for embedded cores and debug of embedded software all require test control at the chip level.
Boundary scan is well-known standard DFT technique (IEEE Std 1149.1 (JTAG)) that simplifies IC testing by placing boundary scan registers between pads and internal logic to provide a standard chip and board test interface. The boundary scan uses a serial scan chain to access the chip I/Os on board. Since the scan chain passes through all the input and output pads of a chip, its inputs and outputs are accessible from the board for sampling data from the other chip and updating data to another chip simultaneously. The resulting boundary-scan chain and other test features of the device are accessed through a standard interface, the JTAG Test Access Port (TAP).
As stated above, the RapidChip platform defines the total number of configurable I/Os, diffused memory, and IP resources for each available slice. This allows most of the test logic to be integrated into the slices before the customer customizes the RapidSlice platform. The RapidBuilder tool also generates a top-module RTL that includes boundary scan cells, an I/O tree for testing, and a JTAG TAP controller that can launch and monitor BIST tests for any diffused coreware or memory in the RapidSlice platform.
Thus, during customization using RapidChip, a customer creates a slice instance that will have a set of coreware diffused on the slice, where each coreware includes embedded boundary scan segments. If some of these coreware are not used during instance creation (a customer design) then there is no need to test these embedded boundary scan segments.
Several third party test synthesis tools are available that solve this problem by automatically implementing the boundary scan circuitry and board-level interface. These tools can support any boundary scan configuration, including user-defined or private instructions, and can be used to make sure that unused embedded boundary scan segments are not tested.
For custom IC's that are designed, tested and manufactured by the same entity, running the third party tools that do the boundary scan synthesis and stitching is not a problem since the entity has a license to use the tools. However, in RapidChip flow, all of the different customers that will use the RapidChip software to create their own instances may not have all the necessary third party tools in-house. And unfortunately, the tools cannot be provided to the customers because the customers may be unwilling to obtain the necessary licenses. Thus, there currently is no option to run third party tools which perform the boundary scan synthesis and stitching in RapidChip.
The problem is how to handle unused coreware having embedded boundary scan segments at the instance level without running third party tools, and still use all the files which are generated at slice creation time. A related problem is how to reuse pre-built Memory Bist and JTAG test structures to avoid the need to use a boundary scan synthesis tool during Rapidchip instance creation.
Accordingly, what is needed is a method and system for handling those unused coreware having embedded boundary scan segments in a slice without running third party boundary scan synthesis and stitching tools, while still using all the files that are generated at slice creation time. The present invention addresses such needs.